1. Field of the Invention
The present invention relates generally to an amplification gain adjusting circuit and particularly relates to an amplification gain adjusting circuit which adjusts the gain of an amplifier driven by a signal power supply by changing a voltage dividing ratio of a resistance type voltage divider by a switching operation of a transistor.
2. Background Art
FIG. 7 shows a known amplification gain adjusting circuit of the kind as described above which is illustrated by way of example. As illustrated, the circuit is applied to an amplifier used in mobile audio equipment. In the drawing, an audio signal input terminal 1 is connected to a non-inverted input terminal of an operational amplifier 2. Generally, when the amplification gain adjusting circuit is used for the amplifier in mobile audio equipment, a bias voltage (+B/2) which is one-half of a supply voltage (+B) is produced by a bias voltage producing circuit 3 and supplied to the non-inverting input terminal of the operational amplifier 2 through a resistor R.sub.1. This extra input is used because the amplifier is generally operated by a single power supply (a battery) and the AC output of the amplifier 2 oscillates around the DC bias of +B/2. An output terminal of the operational amplifier 2 is connected to a signal output terminal 4 as well as to an inverted input terminal of the operational amplifier 2 through a resistor R.sub.2.
A bias cut-off capacitor C.sub.1 and resistors R.sub.3 and R.sub.4 are connected in series between the inverted input terminal of the operational amplifier 2 and ground (zero potential), and a switching transistor Q.sub.1 is connected in parallel to the resistor R.sub.4. The supply voltage (+B) is selectively applied to the base of the transistor Q.sub.1 through a switch S for controlling the turn-on and turn-off of the transistor Q.sub.1. This switched supply voltage (+B) is supplied through a resistor R.sub.5 to the base of the transistor Q.sub.1 for controlling the base current of the transistor Q.sub.1. A resistor R.sub.6 and a capacitor C.sub.2 are connected in parallel between the base of the transistor Q.sub.1 and ground, and this parallel RC circuit provides a time constant to fluctuations in the DC voltage of the battery at the signal output terminal 4 when the transistor Q.sub.1 is turned on or off, so as to reduce noise. The resistor R.sub.6 also acts to maintain the base potential of the transistor Q.sub.1 at the ground level to thereby prevent a misoperation of the transistor Q.sub.1 from occurring when the switch S is in the opened state.
Next, description will be made as to the operation of the thus arranged amplification degree adjusting circuit.
Assume that an AC input signal (E.sub.i =Ae.sup.j.omega.t) is applied to the non-inverted input terminal of the operational amplifier 2 through the signal input terminal 1. When the switch S is in the opened state, an AC output signal E.sub.00 (in addition to the DC bias of +B/2) derived at the signal output terminal 4 is expressed by the following equation because the transistor Q.sub.1 is in the off-state. ##EQU1##
When the switch S is in the closed state, on the other hand, an output signal E.sub.0S generated at the signal output terminal 4 is expressed by the following equation because the transistor Q.sub.1 is in the on-state so that the resistor R.sub.4 is shorted. ##EQU2##
Therefore, a ratio (E.sub.0S /E.sub.00) is as follows: ##EQU3##
In the thus arranged conventional amplification gain adjusting circuit, the DC collector potential of the switching transistor Q.sub.1 is set to ground. Therefore when an instantaneous base-collector forward voltage (V.sub.F) is applied across the collector and base of the transistor Q.sub.1 in the opened stage of the switch S, current begins to flow through the base. That is, when the AC component at the collector of the transistor Q.sub.1 is less than -V.sub.F, a current may flow from ground into the collector through the base-collector path of the transistor Q.sub.1 and the parallel circuit of the resistor R.sub.6 and the capacitor C.sub.2. The result is equivalent to a reduction in the resistance value R.sub.CE of the collector-emitter path of the transistor Q.sub.1 in its off-stage, so that the output waveform appearing at the signal output terminal 4 becomes vertically asymmetrical as shown in FIG. 9.
In order to eliminate the foregoing disadvantages, there has been proposed an amplification gain adjusting circuit as shown in FIG. 10, which is provided with a buffer circuit of a transistor Q.sub.2, resistors R.sub.6 and R.sub.7, and a capacitor C.sub.2. In the thus arranged amplification gain adjusting circuit, however, there arises another disadvantage in the increase in the number of parts as well as generation of pop noises upon turning a switch S off because a time constant cannot be provided at that time.